In the end we have to design the circuit in some simulation program ( we use ISE from Xilinx, wich is free for the most part).

We need to implemente a circuit that follows the following:

. It has 4 inputs : ln1 and ln2 (both with 3 bits each) ; EN( enable signal – 1 bit) ; COD ( 1 bit)

. 2 outputs: RES, that will be the result in the output, e EVEN, that indicates if the result is even (the output is ‘1’ if it is indeed even).

 

If the circuit is not enabled( EN=’0’) , the RES will be all ‘1’s . If it is enabled (EN=’1’), COD will say what the RES will be. If COD is ‘0’ , RES will be the sum between ln1 and ln2, if both are even or both are odd . If one is odd and the other is even ,  RES will be the subtraction between  In1 and In2. If COD=’1’, RES will be the sum  (or the subtraction, depending on what was said before this paragraph) if the result is 10 (in decimal) if not 0 (also in decimal).

 

In the end we have to design the circuit in some simulation program ( we use ISE from Xilinx, wich is free for the most part).

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