Verilog or Schematic
It is intended to design and implement a logic circuit for managing the places in a parking lot, disposed in a straight line, that meets the following specifications:
The inputs should be: Sin and Sout (binary signals correspondent to the input and output sensors of the parking lot, respectively), in direct logic, which means that when at “1” a car is being detected by the sensor; PlaceIn and PlaceOut (4-bit binary signals which specify the place in the parking line the car will enter or leave, respectively); and CLR (a control signal, in inverse logic, that allows resetting the output signals to their initial state);
The parking lot capacity is 10 places in straight line; The entries are for the whole day, which means that for each car entering the park 4€ will be deposited in the cash register. Please assume that at most 15 cars enter per day.
The circuit produces the following outputs: Open, a signal that enables an input light sign to inform drivers that there still are available places; Almost_Full, a signal that enables an input light sign to inform drivers that the park is almost full (less than 3 places available); Nr_Places, a sign that indicates the total number of available places; Profit, a signal that expresses the amount of Euros present in the cash register since the beginning of simulation; and Places, a 10-bit signal that expresses the available places (“0”) and the ones that are occupied (“1”).
Please assume that each clock period corresponds to 1s; When a car reaches the sensors, the entry/leaving process takes 5s to occur (which means that in the meanwhile new entries or leavings should not be taken into account even if the sensor remains active).
It should be done using ISE software from Xilinx, in which you can use both electrical schematic by the logic gate level (advanced functions are not allowed to be used), and Verilog, and tested in simulation.
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